HSTL Based Energy Efficient Vedic Multiplier Design on 28 nm FPGA Using Vedic Formula Adyamadyenantya
نویسندگان
چکیده
منابع مشابه
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam– Vedic method for multiplication which strikes a diff...
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Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutr...
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ژورنال
عنوان ژورنال: Gyancity Journal of Engineering and Technology
سال: 2015
ISSN: 2456-0065
DOI: 10.21058/gjet.2015.1204